| Unit - 1 Minimization Technique |
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| 1.1 Logic Design Minimization Technique Minimization of the Boolean function using Kmap up to 4 variables and Quine McClusky Method |
| 1.2 Representation of signed number signmagnitude representation |
| 1.3 1’s complement and 2’s complement form red marked can be removed |
| 1.4 Sum of product and Product of sum form |
| 1.5 Minimization of SOP and POS using Kmap |
| Unit - 2 Combinational Logic Design |
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| 2.1 Code converter BCD Excess 3 Gray code Binary Code |
| 2.2 Half Adder Full Adder Half Subtractor Full Subtractor Binary Adder IC 7483 BCD adder |
| 2.3 Look ahead carry generator |
| 2.4 Multiplexers MUX MUX IC 74153 74151 |
| 2.5 Cascading multiplexers |
| 2.6 Demultiplexers DEMUX Decoder IC 74138 IC 74154 |
| 2.7 Implementation of SOP and POS using MUX DMUX Comparators 2 bit |
| 2.8 Parity generators and Checker |
| Unit - 3 Sequential Logic Design |
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| 3.1 Flip Flop SR JK D T |
| 3.2 Preset Clear |
| 3.3 Master Slave JK Flip Flops |
| 3.4 Truth Tables and Excitation tables |
| 3.5 Conversion from one type to another type of Flop Flop |
| 3.6 Registers SISO SIPO PISO PIPO Shift Registers Bidirectional Shift Register |
| 3.7 Ring Counter |
| 3.8 Universal Shift Register Counters Asynchronous Counter Synchronous Counter BCD Counter Johnson Counter Modulus of the counter IC 7490 |
| 3.9 Synchronous Sequential Circuit Design Models Moore and Mealy State diagram and State Table Design Procedure |
| 3.10 Sequence Generator and a detector |
| Unit - 4 Algorithmic State Machines and Programmable Logic Devices |
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| 4.1 Algorithmic State Machines Finite State Machines FSM and ASM ASM charts notations construction of ASM chart and realization for sequential circuits |
| 4.2 PLDS PLD ROM as PLD Programmable Logic Array PLA Programmable Array Logic PAL |
| 4.3 Designing combinational circuits using PLDs |
| Unit - 5 Logic Families |
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| 5.1 Classification of logic families Unipolar and Bipolar Logic Families |
| 5.2 Characteristics of Digital ICs Fanin Fanout Current and voltage parameters |
| 5.3 Noise immunity |
| 5.4 Propagation Delay |
| 5.5 Power Dissipation |
| 5.6 Figure of Merits |
| 5.7 TransistorTransistor Logic Operation of TTL NAND Gate Two input TTL with active pull up TTL with open collector output Wired AND Connection Tristate TTL Devices TTL characteristics |
| 5.8 CMOS CMOS Inverter CMOS characteristics CMOS configurations Wired Logic Opendrain outputs |
| Unit - 6 Introduction to Computer Architecture |
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| 6.1 Introduction to Ideal Microprocessor – Data Bus Address Bus Control Bus. |
| 6.2 Microprocessor based Systems – Basic Operation Microprocessor operation Block Diagram of Microprocessor |
| 6.3 Functional Units of Microprocessor – ALU using IC 74181 4bit Multiplier circuit using ALU and shift registers. |
| 6.4 Memory Organization and Operations |
| 6.5 Digital circuit using decoder and registers for memory operations. |